Projects

• Fast and Low-Power Quantized Fixed Posit High Accuracy DNN Implementation (Jan 2021 - May 2021)
  • To overcome the drawback of standard IEEE-754 representation used to represent floating point numbers, we have analysed the effectiveness of using Posit number system by quantising the weights and biases of 8 different DNN in Posit and Fixed-posit formats.
  • It is observed that accuracy remains within the range of 0.3% and 0.57% of Top-1 accuracy for Posit and Fixed-posit representation.
  • Posit based multiplier requires higher PDP and area, whereas, Fixed-posit reduces PDP and area consumption by 71% and 36%, respectively.
• BRAD: Biased Restoring Array Dividers for Error Resilient Applications (Jan 2021 - Mar 2021)
  • Proposed four different controlled approximate subtractor units biased towards borrow bits (BCSUs) that have a maximum of only one error in the borrow bits of the subtractor.
  • We have replaced CSUs with BCSUs using three different replacement strategies – horizontal, vertical, and triangular and analysed the effect of these on different image processing applications.
  • Developed Automation framework using Python and Bash to analyse and compare 288 different designs of Dividers.
• Homo-8T: Homogeneous Energy-Efficient Mixed-VT SRAM Design Techniques for Mobile Video Decoder and Neural Network (Apr 2021 - Jun 2021)
  • Analysed the effect of using Approximate Memory cells on the accuracy of 5 DNN, by using approximate memory to store the weights and biases of neural network.
• Chip Tapeout - UMC65 (Jun 2020 - Jul 2020)
  • Designed and tested 2-stage 32-bit Synchronous processor with integrated SIPO and PISO at the input and output to decrease the number of pins required to access the processor.
  • Designed architecture level schematic for the entire processor part, which includes Synchronous and three other versions of Radiation Hardened processors.
  • Synthesized the full chip in UMC65 technology node and performed Place and Route for the design (RTL to GDS).
• 2-Stage RISC-V Processor (Jan 2020 - Mar 2020)
  • Design of Split Arithmetic and Logic Unit with RISC-V architecture using Bluespec System Verilog.
  • Implemented Multicycle ALU which performs Multiplication and Division using successive addition and subtraction. Flags are provided to stall the pipeline.
  • Working on the design of Approximate multipliers and dividers, which are expected to be more energy efficient compared to exact units. This project is being done under the supervision of Dr. Joycee Mekie.
• Layout on Cadence (Dec 2019)
  • Designed Layouts of 6T,8T SRAM cells and mirror adder circuits.
  • Layout was made in Cadence Layout editor and DRC, LVS and PEX was done using Calibre tool.
• Radiation Hardened 13T and 14T SRAM (Oct 2019 - Nov 2019)
  • Designed 13T and 14T SRAM with improved writing speed, reduced power consumption compared with standard 12T SRAM in Cadence. It is designed for high radiation affected applications.
• 3X3 NOC Router using Verilog (Sep 2019)
• Hybrid Method of Analysis of Shell Lens Antenna (Jan 2017 - Apr 2017)